Saturday, April 11, 2015

MSP430 - setting up the clock

All the microcontrollers needs a clock signal to work.
The MSP430 family is not an exception and actually there are many choices when we talk about the clock.
It is important ALWAYS to have handy the LATEST MSP430 family document and the specific chipset documentation, for example the MSP430F20x2 family (an entry level).
Some schematics/pictures shown here are copied from the MSP430 family document.

Let see the MSP430 clock system

The first thing that come up from the picture above, is that we have three different clock signal generated:
  • MCLK
  • ACLK
Let start from here.


The most important signal generated is the MCLK, the Main System Clock.
As the name imply, this is the clock signal used by the core of the MSP430 chipset, the CPU and basic signals (memory bus/I/O bus/ecc.).


The SMCLK signal is the Sub system clock.
It is normally connected to the peripherals, like the Timer, Watchdog and every peripheral that can require a clock.


The ACLK is an Auxiliary clock.
Sometime it can be necessary to have peripherals using different clocks. For example a UART can require a special timing if compared with the other peripherals or a specific timer needs a low and precise timing.
The Auxiliary clock cannot use the DCO oscillator. It can use only the crystal oscillator.

Clock sources

When the chip is turned ON, i.e. after a hard reset, the clock subsystem is set to generate an approx. 800 kHz signal on the MCLK and SMCLK pin.
This allows the chipset to be able to start to execute instructions. A default clock mechanism must be present otherwise it would be impossible to "program the clock subsystem" if no instructions can be executed.
By default, the source for the SMCLK is the same of the MCLK, the DCO generator.
There are four  possible sources for the clock:

  • Very low frequency clock
  • DCO
  • Crystal oscillator 1
  • Crystal oscillator 2
Some chipset could have only one crystal oscillator, so is important to know what chipset you are using.

Very low frequency clock

This clock runs around 12 kHz and it can be used when the chipset is put in low power mode.
It is reasonably precise.


The DCO (Digitally Controlled Oscillator) is the default source of clock for the MCLK and SMCLK.
As the name imply, it is possible to set up this oscillator simply writing the setting in some registers.
Different frequencies can be generated simply changing some register settings.
There are Pro and Cons using the DCO.

  • flexible frequency generator
  • doesn't require ANY external hardware
  • fast
  • less stable and precise than crystal
  • it require a tuning procedure

DCO calibrated values

The DCO uses resistors, external or internal, to  set up a specific frequency.
If the precision of the clock is not an issue, there is no need to worry about using calibrated values for the DCO.
Because the tolerance of the components, each MSP430 needs a different set of resistor values to set up the clock for specific frequencies.
It would be a very time consuming task to use external resistors, figuring out what is the correct value for a specific frequency, but fortunately TI though about that.
Every MSP430 chip has a table containing the calibrated  (values) for the internal resistor array.
Is enough to read the table and acquire the value for the setting needed.
It is also possible to re-write the table for specific needs, as described in this article.

To determine what setting is needed for specific frequency, requires to study the specific chipset datasheet.
For example, for the MSP430f2012 the datasheet has a table indicating what frequency, with quite a tolerance, correspond to different settings of some specific registers.

Looking at the table, the frequencies generated by the DCO have a quite big tolerance.
This why it could be necessary to re-calibrate the DCO values if a more precise frequency is needed.

Crystal Oscillators

As the name imply, these circuits allows to generate a frequency dependent by a crystal.
They are less flexible than the DCO but they can be very precise and stable.
At least one crystal oscillator is present on every MSP430 chipset.

Programming examples

Here some examples about how is possible to set up the MSP430 clock.
The examples are using the MSP430F2012.

Select DCO for ~8 MHz

After a reset, the main source for the clock, especially MCLK, is the DCO.
The default setting is for a middle/low frequency, around 800kHz (800kHz to 1.5 MHz), but the DCO can reach the 16 MHz in some chipsets.
Unless specific needs, is not a good idea to set the DCO for the maximum frequency.
Mainly because more fast the chip run, more current use and more heat is generated, but also because higher is the generated frequency, lower is the stability and precision.
Is a good idea to use a an external crystal if high speed and precision is required.

To determine what frequency to use it is mandatory to read the data sheet of the specific component, because each device has an internal table with some values to use for the DCO.

Said so, a typical DCO setting for about 8 Mhz is this one.

   DCOCTL = 0x60;   

   BCSCTL1 = 0xB3;

   BCSCTL2 = 0x00;

   BCSCTL3 = 0x0C;

The DCOCTL (Digitally Controlled Oscillator Control register) after a reset is set for:

  • Frequency select middle range (value from 0 to 7, set to 3)
  • Modulator section = 0
The setting to 0x60, according to the table above, set the frequency between 6 MHz to 9MHz.

The BCSCTL1 register (Basic Clock Control Register 1) after the reset has the value of 84 hex (1000 0100), i.e. :
  • Crystal Oscillator 2 disabled (OFF)
  • Crystal low frequency mode
  • ACLK signal divided by 1 (i.e. no division)
  • DCO Resistor select = 4 (nominal frequency for DCO)
After the selection (BCSCTL1 = 0xB3 - 1011 0011):
  • Crystal Oscillator 2 disabled (OFF)
  • Crystal low frequency mode
  • ACLK signal divided by 8
  • DCO Resistor select = 3
The BCSCTL2 after the reset is set to zero and no change is made, meaning:
  • source for MCLK = DCO
  • no divider for MCLK (divider = 1)
  • source for SMCLK  = DCO
  • no divider for SMCLK (divider = 1)
  • use internal resistor for frequency selection
The BCSCTL3 after the reset is set to zero:
  • Crystal oscillator 2 range 0 to 4 MHz (not used anyway)
  • 3.2768 kHz crystal selected (not used anyway)
  • 6 pf capacitor selected for crystal (not used anyway)
After the writing (0x0C - 0000 0011)
  • Crystal oscillator 2 range 0 to 4 MHz (not used anyway)
  • 3.2768 kHz crystal selected (not used anyway)
  • 1 pf capacitor selected for crystal (not used anyway)
Note that the first two bits are only reading.

 Classic watch generator

When is necessary to count time for a clock, timer or watch, normally it is used a crystal of 32768-Hz (3.2768 kHz) because is easy to divide this frequency to obtain 1 second.
Of course we don't want the main clock system signal be so slow, this is the typical setting for the ACLK signal.
Let see what we need to be aware and what to do to have the basic clock set on that.
First of all some hardware is required.

  1. connect the crystal
    A 32768-Hz crystal need to be connected to the chipset (pin XIN and XOUT)
    Usually this require also some capacitors other the crystal, but the chipset has them inside
  2. setting the pins
    Because the crystal is physically connected to some chip pins, we need to program the I/O subsystem accordingly.
    i.e. we need to program the pins connected to the crystal to be rerouted to the clock subsystem.
By default, i.e. after a reset, assuming we are using an MSP430F2012, the XIN and XOUT pins are enabled, i.e. by default these pins are used for the crystal oscillator 1.
So no specific programming on the I/O subsystem is necessary to use a crystal.

Then the software.
We need to set up some chipset registers in order to have the clock up and running.

BCSCTL1 |= DIVA_3; /* ACLK/8 */

BCSCTL3 |= XCAP_3; /* 12.5pF cap */

Let see some details.
The BCSCTL1 register (Basic Clock Control Register 1) after the reset has the value of 84 hex (1000 0100), i.e. :
  • Crystal Oscillator 2 disabled (OFF)
  • Crystal low frequency mode
  • ACLK signal divided by 1 (i.e. no division)
  • Resistor select = 4 (nominal frequency for DCO)
So the register controls different parts of the clock subsystem.
The line BCSCTL1 |= DIVA_3; set only the DIVA bits, changing the original value from 0 to 3, setting the divisor of the ACLK signal to 8. i.e. the generated frequency of the ACLK will be divided by 8.  

The BCSCTL3 register after the reset has the value of 00x (the first two bits are to indicate some fault condition so they can have random setting after a reset).
  • Range for Crystal oscillator 2 : 0 to 1 MHz crystal
  • 3.2768 kHz crystal on oscillator 1
  • 1 pf internal capacitor
The bit 2 and 3 select an internal capacitor to be used with an external crystal.
In our example, we use a 12.5 pF internal capacitor so the selection is 3 (11) for these bits, forced with the line : BCSCTL3 |= XCAP_3;

This is enough to have the ACLK signal generated.
The ACLK signal will have a 32768 Hz / 8 = 4096 Hz.
This value is easily used by the timer in order to generate precise and low periods.

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